a power aware cache and register file design space exploration

A Power Aware Cache and Register File Design Space Exploration

Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications

In the future, embedded processors must process more computation-intensive network applications and internet traffic and packet-processing tasks become heavier and sophisticated. Since the processor performance is severely related to the average memory access delay and also the number of processor registers affects the performance, cache and register file are two major parts in designing embedd...

Improving Register File Banking with a Power-Aware Unroller

The complexity of the register file determines the cycle time of high performance wide-issue microprocessors due to the access time and size of this structure. Both parameters are directly related to the number of read and write ports of the register file. Therefore, it is a priority goal to reduce this complexity in order to allow the efficient implementation of complex superscalar machines. T...

eNuRAPID - A Leakage Power and Wire Latency Aware Cache Design

At future technology nodes, leakage power will become an increasingly dominant source of power consumption. On-chip caches, since they account for the largest fraction of on-chip transistors in modern processors, are a primary target for leakage power reduction. Orthogonal to power consumption, the increasing dominance of on-chip wire delay in building low-latency caches will present additional...

An Interpolative Analytical Cache Model with Application to Performance-Power Design Space Exploration

Caches are known to consume up to half of all system power in embedded processors. Co-optimizing performance and power consumption of the cache subsystem is therefore an important step in the design of embedded systems, especially those employing application specific instruction processors. One of the main difficulty in such attempts is that cache behaviors are application as well as cache-stru...

Power-Aware Register Assignment for Multi-Banked Register Files

The multi-banked register file (MBRF) is an effective approach to reduce the complexity for a monolithic register file. In order to apply the multi-banked register file to a low-power microprocessor, we have to design a dynamic voltage scaling (DVS) approach for the MBRF to reduce its power consumption. However, when the temporary values are stored into an MBRF, their distributed storage locati...